Index of /amirmnoohi/linux-6.11.7/drivers/accel/habanalabs/include/goya/asic_reg

 NameLast modifiedSizeDescription

 Parent Directory   -  
 cpu_ca53_cfg_masks.h 2025-01-22 06:53 11K 
 cpu_ca53_cfg_regs.h 2025-01-22 06:53 2.0K 
 cpu_if_regs.h 2025-01-22 06:53 1.5K 
 cpu_pll_regs.h 2025-01-22 06:53 3.6K 
 dma_ch_0_masks.h 2025-01-22 06:53 19K 
 dma_ch_0_regs.h 2025-01-22 06:53 7.7K 
 dma_ch_1_regs.h 2025-01-22 06:53 7.7K 
 dma_ch_2_regs.h 2025-01-22 06:53 7.7K 
 dma_ch_3_regs.h 2025-01-22 06:53 7.7K 
 dma_ch_4_regs.h 2025-01-22 06:53 7.7K 
 dma_macro_masks.h 2025-01-22 06:53 4.0K 
 dma_macro_regs.h 2025-01-22 06:53 6.6K 
 dma_nrtr_masks.h 2025-01-22 06:53 10K 
 dma_nrtr_regs.h 2025-01-22 06:53 8.4K 
 dma_qm_0_masks.h 2025-01-22 06:53 23K 
 dma_qm_0_regs.h 2025-01-22 06:53 6.5K 
 dma_qm_1_regs.h 2025-01-22 06:53 6.5K 
 dma_qm_2_regs.h 2025-01-22 06:53 6.5K 
 dma_qm_3_regs.h 2025-01-22 06:53 6.5K 
 dma_qm_4_regs.h 2025-01-22 06:53 6.5K 
 goya_blocks.h 2025-01-22 06:53 81K 
 goya_masks.h 2025-01-22 06:53 9.9K 
 goya_regs.h 2025-01-22 06:53 3.6K 
 ic_pll_regs.h 2025-01-22 06:53 3.6K 
 mc_pll_regs.h 2025-01-22 06:53 3.6K 
 mme1_rtr_masks.h 2025-01-22 06:53 36K 
 mme1_rtr_regs.h 2025-01-22 06:53 12K 
 mme2_rtr_regs.h 2025-01-22 06:53 12K 
 mme3_rtr_regs.h 2025-01-22 06:53 12K 
 mme4_rtr_regs.h 2025-01-22 06:53 12K 
 mme5_rtr_regs.h 2025-01-22 06:53 12K 
 mme6_rtr_regs.h 2025-01-22 06:53 12K 
 mme_cmdq_masks.h 2025-01-22 06:53 19K 
 mme_cmdq_regs.h 2025-01-22 06:53 4.9K 
 mme_masks.h 2025-01-22 06:53 83K 
 mme_qm_masks.h 2025-01-22 06:53 23K 
 mme_qm_regs.h 2025-01-22 06:53 6.4K 
 mme_regs.h 2025-01-22 06:53 44K 
 mmu_masks.h 2025-01-22 06:53 7.3K 
 mmu_regs.h 2025-01-22 06:53 1.6K 
 pci_nrtr_masks.h 2025-01-22 06:53 10K 
 pci_nrtr_regs.h 2025-01-22 06:53 8.1K 
 pcie_aux_regs.h 2025-01-22 06:53 9.0K 
 pcie_wrap_regs.h 2025-01-22 06:53 11K 
 psoc_emmc_pll_regs.h 2025-01-22 06:53 3.7K 
 psoc_etr_regs.h 2025-01-22 06:53 4.1K 
 psoc_global_conf_mas..>2025-01-22 06:53 25K 
 psoc_global_conf_regs.h2025-01-22 06:53 28K 
 psoc_mme_pll_regs.h 2025-01-22 06:53 3.7K 
 psoc_pci_pll_regs.h 2025-01-22 06:53 3.7K 
 psoc_spi_regs.h 2025-01-22 06:53 5.1K 
 psoc_timestamp_regs.h 2025-01-22 06:53 1.8K 
 sram_y0_x0_rtr_regs.h 2025-01-22 06:53 2.8K 
 sram_y0_x1_rtr_regs.h 2025-01-22 06:53 2.8K 
 sram_y0_x2_rtr_regs.h 2025-01-22 06:53 2.8K 
 sram_y0_x3_rtr_regs.h 2025-01-22 06:53 2.8K 
 sram_y0_x4_rtr_regs.h 2025-01-22 06:53 2.8K 
 stlb_masks.h 2025-01-22 06:53 5.3K 
 stlb_regs.h 2025-01-22 06:53 1.7K 
 tpc0_cfg_masks.h 2025-01-22 06:53 79K 
 tpc0_cfg_regs.h 2025-01-22 06:53 34K 
 tpc0_cmdq_masks.h 2025-01-22 06:53 19K 
 tpc0_cmdq_regs.h 2025-01-22 06:53 5.0K 
 tpc0_eml_cfg_masks.h 2025-01-22 06:53 18K 
 tpc0_eml_cfg_regs.h 2025-01-22 06:53 12K 
 tpc0_nrtr_masks.h 2025-01-22 06:53 10K 
 tpc0_nrtr_regs.h 2025-01-22 06:53 8.4K 
 tpc0_qm_masks.h 2025-01-22 06:53 23K 
 tpc0_qm_regs.h 2025-01-22 06:53 6.5K 
 tpc1_cfg_regs.h 2025-01-22 06:53 34K 
 tpc1_cmdq_regs.h 2025-01-22 06:53 5.0K 
 tpc1_qm_regs.h 2025-01-22 06:53 6.5K 
 tpc1_rtr_regs.h 2025-01-22 06:53 12K 
 tpc2_cfg_regs.h 2025-01-22 06:53 34K 
 tpc2_cmdq_regs.h 2025-01-22 06:53 5.0K 
 tpc2_qm_regs.h 2025-01-22 06:53 6.5K 
 tpc2_rtr_regs.h 2025-01-22 06:53 12K 
 tpc3_cfg_regs.h 2025-01-22 06:53 34K 
 tpc3_cmdq_regs.h 2025-01-22 06:53 5.0K 
 tpc3_qm_regs.h 2025-01-22 06:53 6.5K 
 tpc3_rtr_regs.h 2025-01-22 06:53 12K 
 tpc4_cfg_regs.h 2025-01-22 06:53 34K 
 tpc4_cmdq_regs.h 2025-01-22 06:53 5.0K 
 tpc4_qm_regs.h 2025-01-22 06:53 6.5K 
 tpc4_rtr_regs.h 2025-01-22 06:53 12K 
 tpc5_cfg_regs.h 2025-01-22 06:53 34K 
 tpc5_cmdq_regs.h 2025-01-22 06:53 5.0K 
 tpc5_qm_regs.h 2025-01-22 06:53 6.5K 
 tpc5_rtr_regs.h 2025-01-22 06:53 12K 
 tpc6_cfg_regs.h 2025-01-22 06:53 34K 
 tpc6_cmdq_regs.h 2025-01-22 06:53 5.0K 
 tpc6_qm_regs.h 2025-01-22 06:53 6.5K 
 tpc6_rtr_regs.h 2025-01-22 06:53 12K 
 tpc7_cfg_regs.h 2025-01-22 06:53 34K 
 tpc7_cmdq_regs.h 2025-01-22 06:53 5.0K 
 tpc7_nrtr_regs.h 2025-01-22 06:53 8.4K 
 tpc7_qm_regs.h 2025-01-22 06:53 6.5K 
 tpc_pll_regs.h 2025-01-22 06:53 3.6K